v ishay siliconix spice device model tp0610 k p-channel 60-v (d-s) mosfet characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and sw itching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the ty pical electrical characteristics of the p-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the puls ed 0-v to 10-v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance netw o rk is used to model the gate charge characteristics w h ile avoiding convergence difficulties of the sw itched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact phy sical interpretation of the device. subcircuit model schematic this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. 1 www. vi s h a y .com document number: 73270 s-52635 ? rev . b , 02-jan-06
v ishay siliconix spice device model tp0610k specificat ions (t j = 2 5 c unless ot herwise not e d) pa ra me te r s y m b o l te s t c o n d i t i o n simulated data measu red data unit static gate threshold voltage v gs(t h ) v ds = v gs , i d = ? 250 a 2 . 8 v on-state drain current a i d ( on) v ds = ? 10 v, v gs = ? 10 v 2 . 2 a v gs = ? 10 v, i d = ? 500 ma 3 3 . 1 drain-source on-state resistance a r d s (on) v gs = ? 4.5 v, i d = ? 25 ma 4 . 4 5 . 5 ? forw ard transconductance a g fs v ds = ? 10 v, i d = ? 500 ma 1 7 0 1 8 0 m s diode forw ard voltage a v sd i s = ? 200 ma, v gs = 0 v ? 0.75 ? 0.90 v dy namic b total gate charge q g 0 . 5 0 gate-source charge q gs 0 . 1 2 0 . 1 2 gate-drain charge q gd v ds = ? 30 v, v gs = ? 10 v, i d = ? 500 ma 0 . 1 4 0 . 1 4 nc not e s a. guaranteed by design, not s ubject to production testing. b. pulse test; pulse w i dth 300 s, duty cy cle 2%. 2 www. vi s h a y .com document number: 73270 s-52635 ? rev . b , 02-jan-06
v ishay siliconix spice device model tp0610 k comparison of model wit h measured dat a (t j =2 5 c unless ot herwise not e d) 3 www. vi s h a y .com document number: 73270 s-52635 ? rev . b , 02-jan-06
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